The present invention relates generally to memory systems and more particularly to memory systems which incorporate on-die termination.
A typical memory system includes a memory controller and one or more memory modules (for example, dual in-line memory modules or DIMMs). Each memory module may include a plurality of memory devices (such as a dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), etc.). For example, a DIMM typically has eighteen (18) memory devices divided into two ranks. The first rank, comprised of nine (9) memory devices, is located on the front side of the DIMM and the second rank, also comprised of nine (9) memory devices, is located on the back side of the DIMM.
Data is written to and read from the memory devices under the direction of the memory controller. Commands and addresses are transmitted unidirectionally (i.e., from the memory controller to the memory devices) via a command/address bus. The memory controller typically provides address information via a single command/address bus simultaneously to all of the memory devices in the system. Thus, the command/address bus tends to encounter high capacitive loading. For example in a two rank system, the command/address bus it said to be “two-rank loaded”, in a three rank system, the command/address bus it said to be “three-rank loaded”, etc. It should be apparent to one skilled in the art that for the command/address bus, a “rank” of loading in the current embodiment refers to nine (9) loads (i.e., one load for each memory device).
A subset of the command/address bus may be sent to each individual rank. For example in a two rank system, one copy of the control pins CS#, CKE, and ODT may be connected to rank-0 via one set of leads and another copy of the control pins CS#, CKE, and ODT may be connected to rank-1 via another set of leads. Thus, each copy of the subset of the command/address bus is said to be “single-rank loaded”.
In contrast to the command/address bus, data is transmitted bi-directionally to and from those memory devices addressed by the memory controller via a data bus. Data may be sent to or retrieved from a single memory device. The data bus may include a plurality of byte lanes, each byte lane having a conductor for each bit in a memory device. For example, a memory system may be comprised of two DIMMS each having two ranks (for a total of four ranks). Each rank may be comprised of nine memory devices, each having eight bits (thus, each rank has 8×9=72 bits). Accordingly, the data bus will have nine byte lanes (i.e., one for each memory device in the ranks), each byte lane having eight conductors (one for each bit in a memory device). Each byte lane is connected to all four ranks (e.g., the most significant byte in each rank is connected to a first byte lane, the next most significant byte in each rank is connected to a second byte lane, etc. for each byte in the rank). Accordingly, each byte lane in the instant example is “loaded with four ranks”. It should be apparent to one skilled in the art that for the data bus, a “rank” of loading refers to one (1) pin (i.e., one pin for each memory device on the byte lane). Due to the topography of the data bus and the manner in which data is transmitted, the capacitive loading on the data bus is low compared to the capacitive loading on the command/address bus.
As a result of the differences in capacitive loading between the data bus and the command/address bus, it is possible to transmit the data at a higher rate than the commands/addresses. For example in a DDR SDRAM, data is “strobed” at twice the rate as the commands (i.e., commands are transferred on the rising edge of a command strobe, whereas the data is transferred on both the rising and falling edges of a data strobe).
The memory system may include on-die termination (ODT). Generally speaking, ODT applies a resistance to one or more input/output pads (for example, connected to the data bus) within a memory device. ODT provides termination to reduce bus signal reflections, thereby improving the integrity of the transmitted signal.
Typically, the memory controller independently enables/disables the ODT for one or more ranks of memory devices within the memory system. This ODT scheme may be referred to as pin controlled ODT. For example, the memory controller may use a chip select signal (CS0#) to designate a DIMM's front rank (i.e., rank-0) to complete a read operation and/or a write operation. The memory controller enables the ODT pin for the DIMM's back rank (i.e., rank-1). The back rank receives the ODT command signal and its data bus is terminated (e.g., resistances are applied to one or more input/output pads of the memory devices within the back rank per the ODT signal).
This conventional pin-controlled ODT scheme, however, has several drawbacks. First, additional pin-outs are needed for the memory controller, the DIMM connector, and each memory device. For example, the DIMM has two ODT pins, one for each rank. Each of the DIMMs ODT pins is connected to separate pins on the memory controller so that one rank of the DIMM can receive ODT command signals from the memory controller independently of the DIMM's other rank. Additionally, each memory device in the rank also has an ODT pin that is connected with its associated rank's ODT pin so that each memory device in the rank is terminated at the same time. In addition to the increased number of pin outs, the memory controller of the conventional pin-controlled ODT scheme is required to provide the ODT command signals to the other components of the memory system. Thus, the complexity of the memory controller and the hardware required to operate the memory controller increases, especially as the number of memory modules increases.
Because of the problems encountered with the increased pin count and memory controller complexity, it is desirable to find alternative methods for implementing ODT. “Bus snooping” has been used as an alternative to the pin-controlled ODT scheme. Snooping may be divided into three categories: self-terminating, non-self terminating, and combined self/non-self terminating.
In self terminating snooping, a memory rank inspects the command/address bus and determines whether it is the target of a pending operation (e.g., whether a write or read is intended for the rank). If the memory rank determines that it is the target of a pending operation, snooping is suspended and the operation executed. If the memory rank determines that it is not the target of the pending operation, it may issue its own ODT command (independently from the memory controller) and resistances are applied to one or more input/output pads of the memory devices within the memory rank.
In non-self terminating snooping, a first memory rank inspects the command/address bus and determines whether another memory rank is the target of a pending operation (e.g., whether a write or read is intended for another memory rank). If the first memory rank determines that another memory rank is the target of a pending operation, the first memory rank may issue its own ODT command (independently from the memory controller) and resistances are applied to one or more input/output pads of the memory devices within the first memory rank.
For the combined self/non-self terminating snooping, the first memory rank inspects the command/address bus and determines whether it or another rank are the target of a pending operation. If the first memory rank determines that it is the target of a pending operation, snooping is suspended and the operation is executed. If the first memory rank determines that it is not the target of the pending operation and/or if the first memory rank determines that another rank is the target of a pending operation, it may issue its own ODT command (independently from the memory controller) and resistances are applied to one or more input/output pads of the memory devices within the first memory rank.
The memory system may operate at 1T or 2T. It should be noted that 1T operation refers to a control scheme wherein the commands are asserted for a single clock pulse, whereas 2T operation refers to a control scheme wherein commands are asserted for two consecutive clock pulses. 2T operation is compatible with self-termination because the column select (CS#) signal qualifies the second clock cycle on the command/address bus (i.e., indicates which rank is intended to receive the information in the second clock cycle). However, 2T operation is problematic with the non-self terminating and the combined self/non-self terminating ODT schemes because the first clock pulse in the 2T cycle may be invalid. For example during bus snooping, a first rank may erroneously interpret the presence of a command intended for another rank at the first clock pulse in the 2T cycle, when in actuality the command bus is merely transitioning between states during the first clock pulse in the 2T cycle. FIG. 8 illustrates this problem.
FIG. 8 shows timing waveforms of on-die termination for a memory rank using a prior art SDRAM running at 2T. At to, the chip select signals for rank-0 (i.e., CS#0) and rank-1 (i.e., CS#1) are inactive (i.e., high) and both ranks snoop the command bus. At t1, the command bus (CMD) is transitioning to a READ command sent from the memory controller that is intended for rank-0 (as seen by rank-0 being active at t2). During this transition period, rank-1 may erroneously interpret the presence of a command (e.g., read, write, etc.) when none is intended. Similarly at t6, the command bus is transitioning to a WRITE command that is intended for rank-0 (as seen by rank-0 being active at t7). During this transition period, rank-1 may erroneously interpret the presence of a command (e.g., read, write, etc.) when none is intended. The CS# signal qualifies the second clock in a 2T system, thus CS# must run at 1T. This is possible, however, because CS# has reduced capacitive loading due to the fact that each rank receives a unique CS# signal.
Thus, there exists a need for an apparatus and method for a memory system that overcomes the limitations inherent to the self-terminating ODT scheme and permits 2T operation of the memory system while overcoming the limitations inherent to the non-self terminating and combined self/non-self terminating ODT schemes.